Means for reducing current-gain modulation due to differences in collector-base voltages on a transistor pair

ABSTRACT

In a circuit including a transistor pair feeding separate loads at different load voltages, current gain modulation or Early effect is avoided by employing an operational amplifier to maintain the collector-base voltages of the transistors equal and thereby maintain their alpha current gains equal.

BACKGROUND OF THE INVENTION

This invention relates to circuits using a transistor pair and more particularly to improvements designed to reduce current-gain modulation arising from differences in the collector-base voltages of the two transistors.

Some high precision circuits that use transistor pairs operating at high voltages often suffer from what is termed current-gain modulation. This is also known as Early effect. When the collector-base voltage of a transistor changes, for example, due to varying load conditions, the current gain, particularly the alpha, changes, as does the base emitter voltage that is required to produce a particular current. When two such transistors are operated in a current mirror configuration where the two load currents should always be equal and track each other, such operation is difficult to achieve, particularly where the two transistors operate with different base-collector voltages.

SUMMARY OF THE INVENTION

The invention is particularly directed to improvements in transistor circuits of the kind in which a pair of transistors having their bases connected in common are fed substantially equal constant currents in their respective emitter paths. A load is coupled separately to each collector of the transistors.

In accordance with the invention, means are provided for maintaining the collector-base voltages of the two transistors equal, thereby maintaining their current gains (alpha) equal at all times even under conditions of varying load. In a specific embodiment of the invention, an operational amplifier is coupled between the collectors of the two transistors with current feedback to the collector of the transistor normally having the higher collector-base voltage.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram showing the circuit according to the invention.

FIG. 2 is a schematic diagram showing the circuit of the invention in greater detail.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1 a pair of PNP transistors Q₁ and Q₂ have their bases connected in common to a bias supply V_(BIAS). A first constant current source 10 is connected in the emitter circuit of the first transistor Q₁ providing a first current I₁. A second constant current source 12 is connected in the emitter circuit of the second transistor Q₂ providing a second current I₂. The two currents I₁ and I₂ are equal.

A first load 14 is connected in the output collector circuit of the first transistor Q₁, and a second load 16 is connected in the output collector circuit of the second transistor Q₂. The second load voltage V₃ is assumed to be more negative than the first load voltage V₁. Under these conditions and in the absence of the invention the voltage V₂ at the collector of the second transistor Q₂ would be greater than the voltage V₁ at the collector of the first transistor Q₂, the two base voltages being equal. Since the transistors Q₁ and Q₂ would have different collector-base voltages, they would also have different alpha current gains, thereby giving rise to the current gain modulation effects already discussed.

In order to overcome these objectional effects, an operational amplifier 18 is connected to the collector outputs of the transistors Q₁ and Q₂ and the output of the amplifier 18 is fed back to the collector of the second transistor Q₂, which has the higher collector-base voltage V_(cb). In particular, the collector of the first transistor Q₁ is coupled to the inverting or negative input of the amplifier 18, and the collector of the second transistor Q₂ is coupled to the non-inverting or positive input. The output of the operational amplifier 18, is coupled to the base of the buffer amplifier Q₃, the emitter of which is coupled to the second load 16, and the collector of which is coupled to the collector of the second transistor Q₂.

The operational amplifier 18 serves to maintain the collector voltages V₁ and V₂ equal and thus equalizes the respective current gains (alpha). Thus even though the base collector voltages and current gains may vary, the amplifier 18 forces them to track each other and keep them equal.

The collector current of the buffer amplifier Q₃ will be equal to the current in the collector of the second transistor Q₂ since the input bias current of the operational amplifier can be made so small as to be negligible. The emitter current of the buffer amplifier Q₃ will differ from its collector current, but the so-called early effect of an NPN transistor such as Q₃ is much less than that of a PNP transistor such as Q₂. The overall effect of this circuit arrangement is that the output current fed to the second load 16 from the emitter of the buffer amplifier Q₃ is independent of the second load voltage V₃.

FIG. 2 is a schematic diagram showing the circuit of the invention in greater detail. An input control current I_(SIG) from a current generator 20 is fed to a PNP bias transistor Q₄ and emitter resistor R₁. The voltage on the base of the bias transistor Q₄ provides the bias for the PNP transistors Q₁ and Q₂, whose bases are connected in common with the base and collector of transistor Q₄. The equal emitter currents I₁ and I₂ of transistors Q₁ and Q₂ flow through emitter resistors R₃ and R₂ respectively.

The output of first transistor Q₁ is fed to a buffer amplfier consisting of three NPN transistors Q₁₀, Q₁₁, Q₁₂ to provide the high output current by the first load 14. The bases of transistors Q₁₁ and Q₁₂ are connected together and to the emitter of buffer transistor Q₁₀. The emitters of transistors Q₁₀, Q₁₁ and Q₁₂ are coupled through resistors R₈, R₇ and R₉ to the first load 14. The collectors of transistors Q₁₀ and Q₁₂ are connected together and to ground. The base of transistor Q₁₀ and the collector of transistor Q₁₁ are coupled to the collector of the first transistor Q₁ to receive the collector current of the first transistor, the voltage V₁ at that point being the collector voltage of the first transistor Q₁.

In the buffer amplifier the majority of the output current of the first transistor Q₁ is sunk by transistor Q₁₁ and resistor R₇. The voltage on the base of Q₁₁ provides bias to the high current transistor Q₁₂. This causes the majority of the current in the output current mirror, which consists of transistors Q₁₀, Q₁₁ and Q₁₂, to flow through transistor Q₁₂ and resistor R₉. The buffer transistor Q₁₀ serves to keep the base current of transistors Q₁₁ and Q₁₂ from loading the collector current of the first transistor Q₁.

The collector outputs of the transistor pair Q₁ and Q₂ are coupled to transistors Q₉ and Q₆, respectively, which at their respective inputs have their bases and collectors connected together. The transistors Q₉ and Q₆ provide the differential input for the operational amplifier 18 shown in FIG. 1. Transistor Q₉ provides the negative or inverting input, and transistor Q₆ provides the positive or non-inverting input. The output of the operational amplifier is taken from the collector current of a transistor Q₇, whose base is connected to the base of transistor Q₆ which is the positive input. A transistor Q₈ having its base connected to the base of transistor Q₉, which is the negative input, serves as a balancing transistor. Resistors R₄, R₅, R₅ ' and R₆ are coupled from a common connection to the respective emitters of transistors Q₆, Q₇, Q₈ and Q₉ and provide emitter ballasting.

Three transistors Q₁₆, Q₁₇ and Q₁₈ provide bias current to the operational amplifier. A current source 22 supplies bias current to the common bases of the transistors Q₁₆, Q₁₇, Q₁₈. Resistors R₁₃, R₁₄, R₁₅ connect the respective emitters of the transistors Q₁₆, Q₁₇, Q₁₈ to a source of potential, such as a battery, which in the case of the NPN transistors is a negative supply.

The equivalent of the buffer amplifier Q₃ of FIG. 1 is provided by three transistors Q₁₃, Q₁₄, Q₁₅. Resistors R₁₀, R₁₁ and R₁₂ couple the respective emitters of the transistors Q₁₃, Q₁₄, Q₁₅ to the second load 16.

The output collector current of the transistor Q₇ of the operational amplifier is coupled to one collector and base of a PNP transistor Q₅, which serves as a level shifter; that is, by means of transistor Q₅, the positive voltage at the collector of transistor Q₇ is shifted down to the negative voltage at the base of transistor Q₁₅ and the collector of transistor Q₁₆. The collector output of the transistor Q₅ in turn drives the base of transistor Q₁₅ in the buffer amplifier. The emitter output of transistor Q₁₅ in turn drives the bases of the output transistor Q₁₄ and the feedback transistor Q₁₃. The emitter currents of the output transistor Q₁₄ and the feedback transistor Q₁₃ are fed to the second load 16. The collector current of the feedback transistor Q₁₃ is fed back to the collector of the second transistor Q₂ and to the base of transistor Q₆, which is the positive input of the operational amplifier.

The collector current of the feedback transistor Q₁₃ is approximately equal to the collector current of the second transistor Q₂. More importantly, the voltage V₂ on the collector of the second transistor Q₂ is equal to the voltage V₁ on the collector of the first transistor Q₁, thereby rendering the alpha current gains of the transistors Q₁ and Q₂ equal and avoiding the Early effect mismatch. 

What is claimed is:
 1. A transistor circuit, comprising:(a) a pair of transistors each having an emitter, base and collector, with their bases connected in common, (b) current supply means for supplying substantially equal current to the emitters of said transistors, (c) a load coupled separately to each collector of said transistors, and (d) means coupled between the collectors of said transistors and between the collector of one of said transistors and the load coupled thereto for maintaining the collector-base voltages of said transistors substantially equal and their current gains substantially equal.
 2. The invention according to claim 1, wherein the means in (d) comprises an operational amplifier having its separate inputs coupled to the respective collectors of said transistors and its output coupled to one of said loads and to the collector of the transistor feeding said one load.
 3. The invention according to claim 2, wherein the output of said operational amplifier is coupled to the collector of the transistor noramlly having the higher collector-base voltage.
 4. The invention according to claim 3, wherein the non-inverting input of said operational amplifier is coupled to the collector of said one transistor and the inverting input thereof is coupled to the other transistor. 